The ATCA-PTSW-AMC4-RTMO is a xTCA[1] based module that follows the specifications presented in PICMG[2]^® PhysRTM.0, Revision 1.0 Draft 0.1g that complements PICMG^® 3.0, Revision 3.0[3] with respect to ARTM specification.

The module acts as a passive External multiple-Host to ATCA Base carrier interface, providing the required electrical and logical connections, with status information.

The module implements the following functions:

• Four PCI Express 4 lane over fibre cable, compliant with v1.x., operating as a downstream system using ATCA Base carrier with a PCIe bay. The PCIe lanes are mapped on ATCA Base Carrier according Table 2.
• Two Gigabit Ethernet ports that are mapped on ARTM connector according Table 3.
• Three General purpose Optical interfaces[4] using SFP (Small form-factor pluggable) connector. These ports are mapped on ARTM connector according Table 4.
• External timing and trigger features connector.
• The ARTM provides features for control and status of on-board devices that are mapped on the ARTM, according tables referenced above.

 

 

Figure 1. ATCA-PTSW-AMC4-RTMO Diagram.

 

This connector follows specifications of AdvancedTCA Rear Transition Module Zone 3A, PICMG® 3.8, R1.0 D0.9 from 9 March 2011.

SCL_L and SDA_L of this connector implement a two-wire interface from the carrier board to the ARTM devices.

Table 1. Power/Management Connector Pin (see Table 2-1 of specification).

 

 

The Fabric connector follows AdvancedTCA Rear Transition Module Zone 3A, PICMG® 3.8, R1.0 D0.9xc from 3 May 2011 that points out to PICMG^®3.3 Revision 3.0 AdvancedTCA^® Base Specification and auxiliary documents.

The RP31 ARTM may or may not be assembled. There is no internal connection for this connector.

 

Table 2. PCI Express lanes mapping on the ARTM connector and corresponding Host Assignment.

Con	Pin	Signal	Fiber Host		Con	Pin	Signal	Fiber Host
			Lane					Lane
Rp33	F1	Port_0_Tx-	L#0	Host #0	Rp33	F5	Port_8_Tx-	L#0	Host #2
Rp33	E1	Port_0_Tx+			Rp33	E5	Port_8_Tx+
Rp33	H1	Port_0_Rx-			Rp33	H5	Port_8_Rx-
Rp33	G1	Port_0_Rx+			Rp33	G5	Port_8_Rx+
Rp33	B1	Port_1_Tx-	L#1		Rp33	B5	Port_9_Tx-	L#1
Rp33	A1	Port_1_Tx+			Rp33	A5	Port_9_Tx+
Rp33	D1	Port_1_Rx-			Rp33	D5	Port_9_Rx-
Rp33	C1	Port_1_Rx+			Rp33	C5	Port_9_Rx+
Rp33	F2	Port_2_Tx-	L#2		Rp33	F6	Port_10_Tx-	L#2
Rp33	E2	Port_2_Tx+			Rp33	E6	Port_10_Tx+
Rp33	H2	Port_2_Rx-			Rp33	H6	Port_10_Rx-
Rp33	G2	Port_2_Rx+			Rp33	G6	Port_10_Rx+
Rp33	B2	Port_3_Tx-	L#3		Rp33	B6	Port_11_Tx-	L#3
Rp33	A2	Port_3_Tx+			Rp33	A6	Port_11_Tx+
Rp33	D2	Port_3_Rx-			Rp33	D6	Port_11_Rx-
Rp33	C2	Port_3_Rx+			Rp33	C6	Port_11_Rx+
Rp33	F3	Port_4_Tx-	L#0	Host #1	Rp33	F7	Port_12_Tx-	L#0	Host #3
Rp33	E3	Port_4_Tx+			Rp33	E7	Port_12_Tx+
Rp33	H3	Port_4_Rx-			Rp33	H7	Port_12_Rx-
Rp33	G3	Port_4_Rx+			Rp33	G7	Port_12_Rx+
Rp33	B3	Port_5_Tx-	L#1		Rp33	B7	Port_13_Tx-	L#1
Rp33	A3	Port_5_Tx+			Rp33	A7	Port_13_Tx+
Rp33	D3	Port_5_Rx-			Rp33	D7	Port_13_Rx-
Rp33	C3	Port_5_Rx+			Rp33	C7	Port_13_Rx+
Rp33	F4	Port_6_Tx-	L#2		Rp33	F8	Port_14_Tx-	L#2
Rp33	E4	Port_6_Tx+			Rp33	E8	Port_14_Tx+
Rp33	H4	Port_6_Rx-			Rp33	H8	Port_14_Rx-
Rp33	G4	Port_6_Rx+			Rp33	G8	Port_14_Rx+
Rp33	B4	Port_7_Tx-	L#3		Rp33	B8	Port_15_Tx-	L#3
Rp33	A4	Port_7_Tx+			Rp33	A8	Port_15_Tx+
Rp33	D4	Port_7_Rx-			Rp33	D8	Port_15_Rx-
Rp33	C4	Port_7_Rx+			Rp33	C8	Port_15_Rx+
Rp33	F9	CPERST#	Reset All Hosts		Rp32	F9	PRSNT#	At least One Host Present
Rp32	E9	WAKE#	Interrupt from Any Host		Rp32	H9	PWRON	Low Power Mode (All Hosts). Set to LOW.
Rp33	H9	RTM_FCLKA-	Not Connected		Rp33	G9	RTM_FCLKA+	Not Connected

 

Table 3. Giga-bit Ethernet mapping (SFP Connector) on the ARTM connector.

Con	Pin	Signal	Description	Interface[5]
Rp33	B9	GbE_Port_0_Tx-	Gigabit Transmit Signal-pair	AMC #1 Site
Rp33	A9	GbE_Port_0_Tx+
Rp33	D9	GbE_Port_0_Rx-	Gigabit Receiver Signal-pair
Rp33	C9	GbE_Port_0_Rx+
Rp32	B9	RTM_SFP_TX_DISABLE_1	SFP Transmit Disable
Rp32	A9	RTM_SFP_LOS_1	SFP Loss of Signal (*)
Rp32	F7	GbE_Port_1_Tx-	Gigabit Transmit Signal-pair	FPGA Ethernet Port #0
Rp32	E7	GbE_Port_1_Tx+
Rp32	H7	GbE_Port_1_Rx-	Gigabit Receiver Signal-pair
Rp32	G7	GbE_Port_1_Rx+
Rp32	D9	RTM_SFP_TX_DISABLE_2	SFP Transmit Disable
Rp32	C9	RTM_SFP_LOS_3	SFP Loss of Signal (*)

(*) Depending on SFP connector used, this signal may not be used.

 

Table 4. Optical SFP connector mapping on the ARTM connector.

Con	Pin	Signal	Description	Interface6
Rp32	B7	IO _Port_1_Tx-	Transmit Signal-pair	FPGA MGT Port #?
Rp32	A7	IO _Port_1_Tx+
Rp32	D7	IO _Port_1_Rx-	Receiver Signal-pair
Rp32	C7	IO _Port_1_Rx+
Rp32	F10	RTM_SFP_TX_DISABLE_3	SFP Transmit Disable
Rp32	E10	RTM_SFP_LOS_3	SFP Loss of Signal (*)
Rp32	F8	IO _Port_2_Tx-	Transmit Signal-pair	FPGA MGT Port #?
Rp32	E8	IO _Port_2_Tx+
Rp32	H8	IO _Port_2_Rx-	Receiver Signal-pair
Rp32	G8	IO _Port_2_Rx+
Rp32	H10	RTM_SFP_TX_DISABLE_4	SFP Transmit Disable
Rp32	G10	RTM_SFP_LOS_4	SFP Loss of Signal (*)
Rp32	B8	IO _Port_3_Tx-	Transmit Signal-pair	FPGA MGT Port #?
Rp32	A8	IO _Port_3_Tx+
Rp32	D8	IO _Port_3_Rx-	Receiver Signal-pair
Rp32	C8	IO _Port_3_Rx+
Rp32	B10	RTM_SFP_TX_DISABLE_5	SFP Transmit Disable
Rp32	A10	RTM_SFP_LOS_5	SFP Loss of Signal (*)

(*) Depending on SFP connector used, this signal may not be used.

 

Table 5. Clock, Trigger and user defined signals mapping on the ARTM connector.

Con	Pin	Signal	Description	Interface6
Rp33	F10	RTM_CLK-	External Clock	FPGA I/O – TCLKB
Rp33	E10	RTM_CLK+
Rp33	H10	RTM_AUX-	User defined	FPGA I/O – TCLKC
Rp33	G10	RTM_ AUX +
Rp33	B10	RTM_IRIG-	IRIG Time Code	FPGA I/O – TCLKD
Rp33	A10	RTM_ IRIG +
Rp33	D10	RTM_TRG-	External Trigger	FPGA I/O – TCLKCA
Rp33	C10	RTM_TRG+
Rp32	G9	RTM_SIGNAL	User defined	FPGA I/O
Rp32	D10	RTM_SPAREIO-	User defined
Rp32	C10	RTM_SPAREIO+

 

The ATCA-PTSW-AMC4-RTMOModule has four Four-Channel, pluggable, parallel, fiber-optic QSFP+ transceivers from Avago Technologies[6].

The PCI Express port mapping into the ARTM fabric connector is depicted in Table 2.

The transceivers can be accessed through a two-wire serial interface that is mapped on the ARTM power connector interface (see section 2.1). Since the ARTM power connector provides a single port a de-multiplexing is implemented (see section 3.1).

Details about transceiver configuration can be found in section 3.2.

 

The RTM_Host Module has two 1000BASE-T 1.25 GBd Small Form Pluggable (SFP) electrical transceivers over Category 5 Cable. The transceivers used are ABCU-5710RZ[7] from Avago Technologies.

These Ethernet ports are mapped into ARTM fabric connector as depicted in Table 3.

The transceivers can be accessed through a two-wire serial interface that is mapped on the ARTM power connector interface (see section 2.1). Since the ARTM power connector provides a single port a de-multiplexing is implemented (see section 3.1).

Details about transceiver configuration can be found in section 3.3.

 

The RTM_Host Module has three Short-Wavelength Pluggable (SFP) Transceivers from Finisar, capable of up to 1.25 Gb/s duplex with a 850 nm VCSEL laser transmitter.

These Gigabit Optical ports are mapped into ARTM fabric connector as depicted in Table 4.

 

The RTM_Host Module includes a connector that may be used for the distribution of several clock signal and general purpose signals. The following table presents the connector pinout.

 

Table 6. Clock and General purpose Connector pinout (J7).

Pin	Signal	Description
1	RTM_TRG-	External Trigger
3	RTM_TRG+
5	RTM_IRIG-	IRIG Time Code
7	RTM_ IRIG +
9	RTM_AUX-	User defined
11	RTM_ AUX +
13	RTM_CLK-	External Clock
15	RTM_CLK+
17	RTM_SPAREIO-	User defined
19	RTM_SPAREIO+
40	SIGNAL	User defined
2, 4, 6, 8, 10, 12, 14, 16, 18, 20	GND	Ground
22, 24	RTM_12V	RTM 12V Power.
26, 28	RTM_3V	RTM 3.3V Power.
30, 32	3V3	Adjustable  power supply (Default 3.3V)
34, 36	VTD25	RTM 2.5V Power.

 

Configurations of ATCA-PTSW-AMC4-RTMOmodule are limited to transmitter/receiver connector/chipsets where protocol and/or physical operation condition may be changed. In addition some features may be used to identify installed infrastructure. The configuration is performed trough the Power and Management plug on Zone 3 (see Table 1).

Status will be available through Led’s on rear panel and on Zone 3 Data Connectors as presented on .

 

 The ARTM configuration uses I2C protocol at address 0x70. The ARTM has two internal devices that may require configuration, which are the two Gigabit Ethernet ports. The access and configuration must be supported by the ATCA Host Board.

Table 7presents the mapping for the I2C switch (PC9548A from NXP Semiconductors^®) with the indication of Control bit register (Figure 2) that enables each port. For detailed information regarding I2C switch PCA9548A data sheet[8] must be consulted.

Table 7. Mapping of ARTM I2C devices into PCA9548A ports.

PCA9548A Port	Control Register bit	ARTM Device
Port #0	Bit-0	PCIeX4 Optical Host #1
Port #1	Bit-1	PCIeX4 Optical Host #2
Port #2	Bit-2	PCIeX4 Optical Host #3
Port #3	Bit-3	PCIeX4 Optical Host #4
Port #4	Bit-4	Ethernet Port (Connected to Carrier FPGA)
Port #5	Bit-5	Ethernet Port (Connected to Carrier AMC Bay #0)
Port #6	Bit-6	Not Used
Port #7	Bit-7	Not Used

 

Figure 2. PC9548A Control bit Register.

.

 

The AFBR-79EQDZ PHY has single address, multiple page memory map architecture accessed through I2C on the base address 0xA0.

The component has a 256-byte address range (starting in 0xA0). The lower 128-bytes are directly accessed. The higher 128-bytes access the selected page (Figure 3). For further details see AFBR-79EQDZ data sheet[9].

 

Figure 3. AFBR-79EQDZ Serial Address Page Structure

 

The ABCU-5710RZ PHY has 32 16-bit internal registers (Table 8) either read-only or Read/Write that can be accessed by I2C on the address 0x31.

 

Table 8. ABCU-5710RZ internal registers mapping (See Data Sheet for details).

There are five status led’s that may indicate Loss Of Signal. Table 9presents LED status description.

 

Table 9. Led Status Indicators.

LED	Description	Status
E1	May indicate Loss Of Signal for Ethernet Port (Eth #01) – Connected to Carrier FPGA.	Not Supported by PHY(Always GREEN)
E2	May indicate Loss Of Signal for Ethernet Port (Eth #02) – Connected to Carrier AMC Bay#0.	Not Supported by PHY(Always GREEN)
D1	May indicate Loss Of Signal for Digital optical Port (Optical #01)	GREEN on Normal Operation
D2	May indicate Loss Of Signal for Digital optical Port (Optical #02)	GREEN on Normal Operation
D3	May indicate Loss Of Signal for Digital optical Port (Optical #03)	GREEN on Normal Operation